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NXP Semiconductors /MIMXRT1011 /ADC_ETC /TRIG2_CHAIN_1_0

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Interpret as TRIG2_CHAIN_1_0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CSEL00HWTS00 (B2B0)B2B0 0IE00 (IE0_EN)IE0_EN 0CSEL10HWTS10 (B2B1)B2B1 0IE10 (IE1_EN)IE1_EN

Description

ETC_TRIG Chain 0/1 Register

Fields

CSEL0

CHAIN0 CSEL ADC channel selection
HWTS0

CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.
B2B0

CHAIN0 B2B 1’b0: Disable B2B, wait until interval is reached 1’b1: Enable B2B, back to back ADC trigger
IE0

CHAIN0 IE 2’b00: Finished Interrupt on Done0 2’b01: Finished Interrupt on Done1 2’b10: Finished Interrupt on Done2 2’b11: Finished Interrupt on Done3
IE0_EN

IRQ enable
CSEL1

CHAIN1 CSEL ADC channel selection
HWTS1

CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.
B2B1

CHAIN1 B2B 1’b0: Disable B2B, wait until interval is reached 1’b1: Enable B2B, back to back ADC trigger
IE1

CHAIN1 IE 2’b00: Finished Interrupt on Done0 2’b01: Finished Interrupt on Done1 2’b10: Finished Interrupt on Done2 2’b11: Finished Interrupt on Done3
IE1_EN

IRQ enable

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data